In an existing data processing system, each synergistic processing unit (SPU) may be interconnected to a host using a network interface card (NIC). The SPU includes configurations such as a central processing unit (CPU) and a memory, and a rear end of the SPU is connected to a magnetic disk. Generally, a field programmable gate array (FPGA) used as an accelerator engine is integrated inside the SPU to assist in work such as data selection or compression.
Generally, the FPGA is disposed between the memory and the CPU. It can be seen that a data flow needs to flow between the CPU, the FPGA, and the memory. In actual application, the CPU, the FPGA, and the memory are generally different in input/output (I/O) bandwidth. Therefore, the data flow between the CPU, the FPGA, and the memory may cause low data processing efficiency.